Parallel Architectures and Computer Vision

A collection of essays based on the proceedings of the first UK workshop involving workers in parallel architectures and computer vision. It was organized by the British Computer Society, and held in Oxford in 1987, bringing together many of the leading researchers in the UK from both industry and academia. The essays discuss the potential offered by solutions to the problem of understanding natural images by computer and the likely effect on society. Robots for advanced manufacturing which control their own actions by vision, autonomous guided vehicles which can manoeuvre around the factory or office, and "electronic guide dogs" for the blind are all examples of current goals of vision research projects. In such "real-time" applications, natural scenes will have to be analyzed and understood in a fraction of a second. However, there is a huge gap between such applications and what is possible now, and such images often have to be of highly stylized scenes to make any analysis possible. It is argued that the future of computer vision will lie in the use of massive parallelism and that the advances now being made in VLSI technology may allow such parallelism to be economically feasible. The work is intended to be of value to researchers in computer vision, parallel computing, robotics, pattern recognition, artificial intelligence and associated subjects.Table of ContentIntroduction. Optimization, regularization and simulated annealing in low-level computer vision; restoration of binary images using networks of analogue neurons; visual reconstruction and the GNC algorithm; improved locally-based recovery of optic flow fields; the PMF stereo algorithm - theory and implementation; the recovery and statistical combination of geometrical descriptions from stereo range data; parallel algorithms for shape representation; locating a known object using a generate and test strategy; RSRE experience implementing computer vision algorithms on transputers, DAP and DIPOD parallel processors; intermediate-level vision, relations and processor arrays - an application of Clip4 to image sequence analysis; a pipelined architecture for a video-rate canny operator used at the initial stage of a stereo image analysis system; a distributed architecture for image processing; the disputer - a dual-paradigm parallel processor for graphics and vision; design and analysis of image processing algorithms for programmable VLSI array processors; the design and implementation of low-level image processing algorithms on a transputer network; designing efficient systolic algorithms for VLSI parallel processor arrays; VLSI and WSI associative string processors for computer vision; mapping images onto processor array hardware; a dynamic, load-balanced, active-data model of parallel processing for vision.